EHU/UPV - SOC4SENSING CHAIR PHD POSITION 3 - NEUROMORPHIC PROCESSING SYSTEMS FOR DYNAMIC VISION SENSORS (DVS)

IKERLAN Ikerlan formamos parte de la corporación Mondragon, la cooperativa más grande del mundo.
Somos un centro tecnológico líder en la transferencia de conocimiento y en la aportación de valor competitivo a las empresas.
Buscamos la excelencia en la I+D+i, a través del aprendizaje diario y la adaptación a las necesidades de nuestros clientes y la cercanía a la realidad empresarial.
Descripción de la oferta The University of the Basque Country (UPV/EHU) SoC4sensing University-Business Chair presents an ambitious Research and Training Plan to develop microelectronics design skills in new generations of electronics engineers.
The SoC4sensing chair is supported by 17 researchers from the APERT and GDED research groups in the UPV/EHU.
It is co-funded by the Spanish Government and private sector companies such as IKERLAN Coop., System-on-Chip engineering S.
..
and the Basque Industry Association of Applied Knowledge and Technologies GAIA.
This chair responds to the motivation of generating new economic activity based on new semiconductor devices that include differential elements for the industrial sectors of which there is a deep knowledge in the region.
This thesis proposal will be developed in collaboration with IKERLAN research center.
IKERLAN is currently launching a new research line on neuromorphic processing systems, covering both sensing and processing stages.
Initial efforts will be aligned with the Horizon Europe NimbleAI project that brings together 19 leading academic and industry EU/UK partners under the coordination of IKERLAN.
NimbleAI will leverage key principles of energy-efficient visual sensing and processing in biological eyes and brains and harness the latest advances in 3D stacked silicon integration, to create an integral sensing-processing architecture that efficiently and accurately runs computer vision algorithms in resource- and area-constrained endpoint chips.
The SoC4sensing Chair is based at the Faculty of Engineering of Bilbao (https://www.
hu.
us/en/web/bilboko-ingeniaritza-eskola/website).
This Faculty is located in the city center of Bilbao, very close to San Mames Stadium and is excellently connected by public transportation.
What will we provide you? A unique collaborative framework to conduct a PhD that includes fully funded enrollment in a leading university in promoting this technology in the regional and national environment and close collaboration with a key high-tech research center.
This ensures that the outcome of the thesis is both innovative and realistic in line with the current state of the technology, as well as applicable to real-world industry products in the short- to mid- term.
Additionally, SoC4sensing Chair offers expert training on SoC VLSI design and funding for the tape-out of developed designs.
We offer a flexible work model and a range of various training opportunities for personal growth.
Your functions will be.
This thesis is aimed at adapting an already developed DVS-based processing pipeline prototyped in FPGA for its implementation in silicon.
The proposed pipeline includes DVS interface with foveation control, event-driven filter, event-to-frame conversion and frame delivery via AXI Stream interfaces and memory-mapped registers for access from a main CPU via AXI.
Pioneering research lines will be explored within the framework of manufacturing this novel technology in silicon for the first time.
Key areas of investigation may include.
- Power consumption optimization, such as analyzing advanced circuit design techniques for low power.
- Performance enhancement, which could be focused on improving the speed and efficiency of event processing in DVS, studying new architectures and parallelization methods to increase processing capabilities, leveraging the asynchronous nature of events generated by the sensors.
Comparative studies could be conducted on the efficiency of DVS processing algorithms implemented in silicon compared to their FPGA counterparts.
This will allow the evaluation of the performance in terms of latency, accuracy, and power consumption, providing a framework for future optimizations and improvements of the pipelines.
The PhD candidate will work in collaboration with other Soc4Sensing candidates in the integration of the DVS pipeline with RISC-V-based SoC designs, and potentially, neural networks accelerators or co-processors to demonstrate joint functioning pre and post tape out.
Requisitos To enjoy this team you will need.
A Master’s degree in Electronic Engineering, Electrical Engineering, Computer Science or equivalent with a background in design of digital circuits using HDL.
Team player with strong analytical, interpersonal, communication, and English language skills.
Background in signal processing, computer vision, machine/deep learning and associated frameworks.
Prior knowledge of neuromorphic architectures (especially relevant are event-based processing) and dynamic vision sensing.
Experience in microarchitecture modelling.
Experience with EDA tools for semiconductor design.