RTL DEVELOPMENT ENGINEER (FPGA EXPERT)

Our client, a leading global IT service provider, is recruiting an RTL Development Engineer (FPGA Expert) to join their project in Spain.Position Title:RTL Development Engineer (FPGA Expert)Position Type:PermanentStart Date:ASAPLocation:Madrid, Spain - no remote workContact:Davor Molnar | +49 (0) 89 23 88 98 63We are seeking an experienced RTL (Register Transfer Level) Development Engineer with expertise in FPGA design and extensive knowledge of Xilinx/AMD tools, including Vivado. The successful candidate will play a critical role in the design, development, verification, and implementation of FPGA-based solutions for complex systems.This role requires a deep understanding of FPGA architecture, RTL design, simulation and synthesis, as well as proficiency in Vivado for hardware design, debugging, and verification.Responsibilities: RTL Design and Implementation:Design, develop, and optimize RTL code in VHDL/Verilog/SystemVerilog for FPGA-based systems.Develop efficient, modular, and reusable RTL architectures for high-performance, low- power, and scalable systems.Implement complex algorithms and digital signal processing (DSP) blocks for FPGA targets.Perform RTL coding for custom IP cores and integration of third-party IP cores as per project requirements.FPGA Synthesis and Place-and-Route::Utilize Xilinx Vivado for synthesis, timing closure, and place-and-route of FPGA designs.Optimize FPGA resource utilization, timing, power, and area to meet design constraints and specifications.Perform static timing analysis (STA) and ensure designs meet timing closure across all operating conditions.Verification and Debugging::Create testbenches and verify RTL designs using simulation tools such as ModelSim, Questa, or Xilinx XSim.Perform pre-silicon verification, including functional and timing verification at RTL and gate-level.Debug designs using simulation, logic analyzers, and in-circuit testing tools such as Vivado ILA (Integrated Logic Analyzer) and Chipscope.Vivado Toolchain Expertise::Utilize Vivado’s IP integrator to build complex FPGA systems using standard and custom IPs. Work with Vivado HLS (High-Level Synthesis) to convert high-level algorithms (C/C++) into RTL for FPGAs.Develop scripts for automation using TCL and other scripting languages within the Vivado environment.Use Vivado’s bitstream generation and device programming tools to configure FPGAs..System-Level Design:Design FPGA-based systems that integrate with microprocessors, DSPs, or custom hardware.Work on SoC platforms such as Zynq/Zynq UltraScale+ by leveraging Xilinx tools to create hardware-software co-designs.Collaborate with firmware, software, and hardware teams to integrate FPGAs into larger systems and platforms.Documentation and Compliance:Create and maintain detailed documentation, including design specifications, block diagrams, and verification plans.Ensure designs are compliant with industry standards and specific project requirements.Work with teams on version control and design management using tools like Git.Collaboration and Leadership:Provide technical guidance and mentorship to junior FPGA engineers.Work closely with cross-functional teams, including hardware, software, and product engineering teams.Communicate effectively with stakeholders to discuss project progress, challenges, and technical decisions.Qualifications required:Education: Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.10+ years of hands-on experience in RTL design for FPGAs, including Xilinx/AMD devices.Extensive experience with Xilinx Vivado Design Suite, including synthesis, simulation, and debugging.Solid understanding of FPGA architecture, timing analysis, and clock domain crossing (CDC) techniques.Expertise in VHDL/Verilog/SystemVerilog coding for RTL design.Experience with FPGA verification methodologies (simulation, constrained random testing, etc.).Preferred Qualifications:Experience with Xilinx Zynq SoC (including Zynq UltraScale+) for hardware-software integration.Proficiency in Vivado HLS (High-Level Synthesis) and familiarity with C/C++ algorithm conversion into hardware.Familiarity with industry standards such as AXI, PCIe, Ethernet, or other high-speed interfaces.Knowledge of FPGA design for signal processing, communication systems, or AI/ML accelerators.Familiarity with TCL scripting and automation in Vivado.Experience with embedded system design and development.Strong problem-solving skills and the ability to troubleshoot complex digital designs.Excellent communication skills, both written and verbal.Ability to work in a team and independently with minimal supervision.Strong attention to detail and ability to document designs and processes thoroughly.