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STAFF PHYSICAL DESIGN ENGINEER / IMPLEMENTATION / ASIC

Descripción de la oferta de empleo

Staff Physical Design Engineer (m/f/d) Location: Barcelona (alternative Portugal or Netherlands)We are looking for a Senior Physical Digital Design Engineer to join our client in one of our offices in Europe (Spain, Portugal or in the Netherlands). This role will be on-site, no remote option is available. The candidate will be responsible for all aspects of physical design and implementation. In this role, you will participate in the efforts of establishing physical design methodologies and flow automation. Physical Design Engineer will be part of the design development team. The candidate will work on the digital design implementation, and verification of mixed-signal ICs utilizing standard EDA tools. Products to be designed/verified include power management and mixed signal functions. If This is, you please continue reading below!ResponsibilitiesResponsible for physical design, development, & verification of digital / mixed-signal IC’sChip & block floorplan/implementation, power/clock distribution, chip assembly, P&R, STA, & LVS/DRC to closureWork closely with digital/analog design team for physical implementation and custom analog blocks/interface/IP’sRequirementsRequires advanced degree in Elec Engineering/Computer Science or equivalent.3-5 years (preferred) of Physical Digital Design experience.2+ years (preferred) ASIC design, verification, or related work experience.Good written/verbal communication English skills and strong teamwork collaborationAbility to work independently, follow instructions according to design specifications and execute tasks to hit milestones with quality.Strong knowledge of ASIC development process and digital design techniques.Experience with programming, scripting and automation languages like Perl/TCL/Unix/Python Strong technical abilities & understanding in these areas:Verilog/System Verilog coding.Synthesis, CTS, DFT, Extraction, and STA closure across multiple process corners.Multipower domain, signal integrity, & power/IR drop analysis.Linting and CDC requirements.Expertise in both hand-written and tool-driven functional/timing ECO.Physical Design Verification methodology to debug LVS/DRC issues at chip/block levelUser of industry physical tools: Cadence Encounter/Innovus tools(preferred) or Synopsys ICC/ICC2.Apply via LinkedIn, or send your CV to lh@eu-recruit.comBy applying to this role you understand that we may collect your personal data, store and process it on our systems. For more information please see our Privacy Notice (https://eu-recruit.com/about-us/privacy-notice
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Detalles de la oferta

Empresa
  • European Recruitment
Localidad
  • En toda España
Dirección
  • Sin especificar - Sin especificar
Fecha de publicación
  • 29/06/2024
Fecha de expiración
  • 27/09/2024
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