DESIGN VERIFICATION ENGINEER

Position: UVM (Universal Verification Methodology) Engineer /Design Verification EngineerLocation: Madrid, Spain (Hybrid)Overview:We are seeking an experienced UVM (Universal Verification Methodology) Development Engineer with expertise in simulation tools like Cadence Xcelium (or similar), to join our verification team. The ideal candidate will have a strong background in creating complex verification environments using UVM and driving the verification of digital designs through simulation. This role is critical in ensuring the functionality, performance, and reliability of ASIC/SoC and FPGA designs in cutting-edge projects.Key Responsibilities:1. UVM Testbench Development:o Develop UVM-based testbenches to verify digital designs (ASICs, SoCs, or FPGAs) at the block, subsystem, and system levels.o Architect, design, and implement reusable verification components such as drivers, monitors, scoreboards, and sequences.o Create constrained-random test environments, functional coverage models, and assertions to ensure comprehensive verification.2. Simulation and Debugging:o Use simulation tools such as Cadence Xcelium, Mentor Graphics Questa, Synopsys VCS, or similar for running simulations and debugging complex designs.o Analyze waveforms, logs, and results to pinpoint issues and resolve design or verificationrelated bugs.o Conduct regression testing, performance analysis, and ensure test coverage goals are met.o Implement code and functional coverage, track metrics, and improve coverage closure.3. Verification Planning and Execution:o Develop detailed verification plans based on design specifications, functional requirements, and target coverage metrics.o Collaborate with design teams to understand the design architecture and define verification strategies.o Execute test cases for various configurations and modes of the design, ensuring adherence to verification goals and milestones.4. UVM Methodology Expertise:o Ensure the use of best practices for UVM development, including adherence to coding standards, object-oriented programming principles, and modularity.o Optimize UVM testbench components for performance, reusability, and scalability.o Mentor junior verification engineers on UVM methodology and best practices, providing guidance on code reviews, debugging, and problem-solving.5. Automation and Scripting:o Develop automation scripts for simulation, regression runs, and reporting using scripting languages such as Python, Perl, or Tcl.o Implement makefiles, run scripts, and automation flows to streamline the verification process and maximize efficiency.6. Assertion-Based Verification (ABV):o Leverage assertion-based verification techniques to capture critical design behaviors and ensure proper functionality.o Work with SystemVerilog assertions (SVA) and other formal verification techniques to complement UVM-based verification.7. Collaborative Development:o Work closely with RTL designers, architects, and systems engineers to understand design intent, review test plans, and resolve issues identified during verification.o Contribute to code reviews, design reviews, and verification reviews to ensure the highest level of quality in the verification process.o Collaborate with cross-functional teams to ensure test environments are aligned with overall project goals and timelines.8. Documentation and Reporting:o Document verification environment architecture, test plans, coverage metrics, and results for internal and external stakeholders.o Provide regular status updates, coverage reports, and detailed bug tracking to the project team and management.o Ensure version control of verification environments and track changes using Git, SVN, or other version control systems.Required Qualifications: Experience:o 10+ years of experience in UVM-based verification for digital IC/ASIC/SoC designs.o Hands-on experience with simulation tools like Cadence Xcelium, Mentor Graphics Questa, Synopsys VCS, or similar.o Proficiency in SystemVerilog for verification, including the development of complex UVM components and test environments.o Experience with writing SystemVerilog Assertions (SVA) and using assertion-based verification.o Proven ability to create, maintain, and execute regression test suites for large-scale digital designs.Preferred Qualifications:• Familiarity with formal verification methodologies and tools such as JasperGold.• Knowledge of functional coverage techniques and strategies to ensure high-quality verification.• Experience with Python, Perl, or Tcl scripting for automation of verification tasks.• Familiarity with industry-standard interfaces such as AXI, PCIe, Ethernet, or DDR.• Experience in low-power verification techniques, using tools like UPF/CPF.• Knowledge of digital design concepts, such as RTL design, synthesis, and timing closure, to better understand verification needs.• Experience with multi-core or multi-processor verification.Personal Attributes:• Strong problem-solving skills and the ability to debug complex designs and test environments.• Excellent communication skills, both written and verbal, for clear reporting and collaboration.• Ability to work independently and in a team, with a proactive approach to resolving issues.• Meticulous attention to detail and a commitment to delivering high-quality verification results.