PRINCIPAL VERIFICATION ENGINEER - TEAM LEAD
Descripción de la oferta de empleo
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SystemVerilog, VerilogAMS); Create DV (Design Verification) test cases, run associated simulations and debug the results; Lead and mentor less experienced DV engineers; Promote cutting-edge DV methodologies and make their use available to the community.
Who we are looking for Successfully completed university degree in Electronics, Electrical Engineering, Physics or comparable; Several years (~7 years) of professional experience in mixed-signal design/verification with hands-on experience with relevant design/simulation tools; Solid knowledge of design verification methods, tools and languages (Digital Mixed-Signal simulation, SystemVerilog, UVM, assertions); Experience in analog block modeling; Analytical mind to solve complex problems and debugging skills; Team-oriented and ability to mentor less experienced engineers; Strong commitment to deadlines and the advancement of the DV discipline; Good communication skills and proficiency in English.
Detalles de la oferta
- ams OSRAM
- 31/10/2024
- 29/01/2025
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